The present invention relates to small computer systems.
The Standard "Parallel Port"
Part of the industry-standard architecture (ISA),.sup.1 which dates back to at least ten years ago, is a definition for a "parallel port" (port "LPT1") which derives from older Cemronics printer standards. The line assignments in this port (detailed below) are not highly parallelized, but do provide a moderately fast rate of data transfer (about 19,200 kbps). The pinout of this port, in the standard DB-25 connector, is shown in FIG. 3. See generally Dowden, INSIDE THE EISA COMPUTER (1990), which is hereby incorporated by reference. FNT .sup.1 See generally, e.g., P. Norton, THE PETER NORTON PROGRAMMER'S GUIDE TO THE IBM PC (1985), which is hereby incorporated by reference.
This port definition is highly standardized, and a parallel port of this type appears on nearly every "ISA" or "EISA" (extended industry-standard architecture) or PS/2 machine, and also on other machines.
In the original IBM PC (a leading prototype of the ISA), the primer port was controlled by LSTTL MSI chips. In more recent machines, this function of port control is typically combined with other functions in a more highly integrated support chip on the computer motherboard.
Observed Problems with the Parallel Port
Many personal computers have experienced problems when a parallel printer is connected to the system. These problems include:
1) The system board fails to cold boot when a printer is connected to the parallel port and turned on. PA1 2) The printer will continuously advance paper if left on after the system is turned off. PA1 3) The printer cannot be taken on or off-line when the computer is turned off. PA1 4) The parallel port and sometimes the serial ports will fail when a primer destroys the I/O chip. The parallel port isolating buffer described resolves these problems by greatly reducing the effects that a parallel device can have on a computer system that is turned off.
As taught by the present application, many of these problem occurrences result from the use of CMOS-technology port interface circuitry, wherein a PMOS pass transistor permits high signal voltages to be passed without incurring a V.sub.T drop..sup.2 However, this PMOS device provides a low impedance path to the printer when the system board is powered off. This low impedance can cause all of the above problems, depending on the particular system board, printer, and other devices installed in the system. FNT .sup.2 For example, if a normal (enhancement-mode) NMOS pass transistor is used as a pass gate to transmit high levels, the drain voltage can only be pulled up to within about one threshold voltage (V.sub.T) of the voltage applied to the gate. This limitation is referred to as "V.sub.T drop." The magnitude of a threshold voltage depends on the particular integrated circuit process parameters used, but is typically in the neighborhood of a volt in modern CMOS processes.
Conversely, a PMOS pass transistor (but not an NMOS transistor) will incur a V.sub.T drop when transmitting low logic levels. Thus, by using NMOS and PMOS transistors back-to-back, and controlling them with opposite logic signals, VT drops can be completely avoided. This configuration is known as a "transmission gate." Use of transmission gates does not avoid the problems noted above, since the PMOS transistor in a transmission gate will be ON whenever the gate voltage drifts down to ground after power is removed.
For example, this problem has been observed in systems using the 16C452 (dual asynchronous communications element) chip, and in systems using the VTI 82C106 chip, and is believed to occur in other systems as well.
Electrical Isolation for the Parallel Port
The invention described solves these problems by isolating four control lines in the standard printer port interface, by preventing the low impedance path seen when the system board is powered off.
Disclosed is a parallel port isolation buffer which, when connected in series with the parallel port, will generally prevent the above problems from occurring. Through the use of eight diodes, four transistors, and four resistors, this buffer isolates the printer control signals from the effects of turning off a computer system.
On each of the buffered lines, a blocking diode permits the computer to pull up the line to the primer. This blocking diode is shunted by a bipolar transistor (NPN, in the presently preferred embodiment). Base current for this bipolar is stolen, through isolation diodes, from whichever of the four buffered lines is high.
The functional definition of the port requires that, during normal operation, one of the control lines will always be high. Thus, during normal operation, there will always be a base current source to turn on the NPNs in the other three buffered lines. Thus, these NPNs provide a low-impedance bidirectional path for handshaking between the computer and the printer.
In the presently preferred embodiment, only four control lines are isolated. This preferred arrangement takes advantage of the peculiarities of the standard port definition (as discussed below) and limits manufacturing cost, while still solving the problems noted above. However, in alternative embodiments, other lines can also be similarly isolated.
Compact Parallel Port Adapter
In the presently preferred embodiment, this buffer is packaged in a male/female printer port adapter, which is connected between the printer cable and the printer port connector on the computer chassis. This adapter has the particular advantage that it can be sold or given users who, for whatever reason, experience power-off parallel port problems.
However, in an alternative class of embodiments, equivalent circuitry can be integrated onto the system motherboard.